TSMC has announced its 1.4nm A14 process technology with second-generation Gate-All-Around (GAA) transistors. The technology will deliver a 10-15% performance gain at the same power consumption, as well as a 25-30% reduction in power consumption while maintaining frequency and logic complexity compared to 2nm N2. Logic density will increase by 23%, and the overall transistor density in a mixed design will be 20%. Volume production is planned for 2028, with a version with back-side power delivery set to debut in 2029.
Image Source: TSMC
At the North American Technology Symposium, TSMC announced that A14 is a new process node designed from scratch, so chip designs designed for previous nodes will not work with it. The new node is built on second-generation nanosheet transistors manufactured using the latest gate-angle-attack (GA) technology. This differentiates it from the N2P node, which is based on the N2 platform, and from A16, which is an improved N2P with a Backside Power Delivery (BSPDN) system. Unlike A16, the base version of A14 does not support the Super Power Rail architecture. This reduces costs, but limits the technology to scenarios that require high power density. However, the lack of BSPDN makes A14 a viable choice for applications where the benefits of this technology are minimal or not noticeable.
Key features of TSMC’s A14 process node compared to N2. Image source: TSMC
Despite the lack of BSPDN, the A14 process maintains high efficiency thanks to the use of second-generation nanosheet transistors. One of the key components of the technology is NanoFlex Pro, an advanced standard cell architecture that gives designers the flexibility to configure logic blocks based on three important metrics: performance, power consumption, and die area (Power, Performance, Area, or PPA). Although the company does not disclose the technical differences between NanoFlex Pro and the previous version of NanoFlex, it can be assumed that it is about advanced DTCO capabilities – design and process co-optimization – as well as more precise tuning at the cell and transistor level.
TSMC High-end and Mainstream Process Node Development Roadmap 2020–2028. Image Source: TSMC
TSMC expects mass production of A14 chips to begin in 2028. However, the company has not yet specified in which half of the year serial production of these chips will begin. Considering that mass production of N2P and A16 process technologies will begin in the second half of 2026, it can be assumed that the production of chips using the A14 technology will be timed to the first half of 2028. The A14 version with the Super Power Rail (SPR) architecture – the back-side power supply system (BSPDN) – is expected in 2029. Although the official name of this modification has not yet been announced, it will probably correspond to the accepted TSMC nomenclature and will be designated A14P.
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A distinctive feature of the A14 is the use of a front-side power delivery system similar to that used in the N2 and N2P process technologies. This makes the architecture particularly suitable for client and specialized computing tasks where high-density power supply routing is not required, but energy efficiency and scalability are critical.
According to TSMC, the A14 process technology targets a wide range of applications, including client devices and edge computing tasks, where high performance is important within power and die area constraints. Due to architectural features and parameters, the A14 technology provides a balance of key PPA metrics in various design scenarios.