In April 2025, at the North American Technology Symposium, TSMC announced that it had begun volume production of chips using the N3P process technology as early as Q4 2024. This third-generation 3nm platform maintains full compatibility with chip designs for the previous 3nm process technology and is targeted at applications where high performance and low power consumption are critical, from consumer devices to data centers.
Image Source: TSMC
N3P technology is an optical compression of the previous N3E process technology. While maintaining the same design rules and compatibility with chip blocks, it provides a performance increase of up to 5% with the same level of leakage currents or a reduction in power consumption by 5-10% at the same frequencies. In addition, in circuits with a standard proportion of logic, SRAM and analog elements (50%, 30% and 20% respectively), N3P provides a transistor density increase of 4%.
The increased integration density in N3P is achieved by improving the optical parameters of the lithographic process rather than by changing the design rules, which facilitates more efficient scaling of all functional structures of the chip. This advantage is especially evident in projects with a predominance of SRAM memory, where high integration density is critical. The process technology is currently used to fulfill production orders for key customers of the company.
TSMC clarifies that the development of the 3nm process line is not limited to the N3P node. The next step will be the 3nm N3X process, which is planned for mass production in the second half of 2025. This version is focused on achieving maximum clock frequencies and, according to internal company estimates, provides a 5% increase in maximum performance at a fixed power consumption or allows for a 7% reduction in power consumption at an unchanged frequency compared to N3P.
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The key difference of the N3X process technology is the support of supply voltage up to 1.2 volts, which is an abnormally high value for a 3-nm process node. This allows the chips to reach the maximum clock frequency (Fmax), which is especially important for client-segment processors. However, this capability is associated with serious technological limitations: the power due to leakage currents can increase by up to 250%. Therefore, when designing N3X-based chips, an engineering compromise is required between performance and thermal parameters of the device.
Kevin Zhang, Senior Vice President of Business Development and Global Sales and Deputy Chief Operating Officer of TSMC, noted that the company continues to optimize its process technologies even after they have transitioned to mass production. According to him, the transition to a new process node requires significant investments from customers, including the development of chips within the ecosystem. Therefore, TSMC’s strategy is aimed at continuously optimizing the technologies already implemented so that customers can maintain the effectiveness of their previous investments for a longer period.
TSMC traditionally releases several iterations of a single process node within a single development kit — Process Development Kit (PDK). An example is the N5 and N4 process technology series, which include N5P and versions of N4P and N4C, respectively. This approach allows the company to use expensive process equipment as efficiently as possible, and customers to reduce costs by reusing IP blocks. N3P and N3X nodes organically continue this strategy within the 3-nm family of process technologies.
Despite the focus on the upcoming 2nm GAA process technology, the bulk of the client processors coming to market in the coming quarters will be manufactured using the N3 family of processes. This includes next-generation smartphones, tablets, and PCs expected to launch in 2025 and beyond.