Modern processors are typically small in size, but the world’s largest contract semiconductor manufacturer TSMC is developing a new version of its CoWoS chip packaging technology that will enable the creation of designs up to 9.5 photomask sizes (7,885 mm²) on 120 x 150 mm (18,000 mm²) substrates. The performance of such giants will be 40 times higher than that of modern processors. But that’s not the limit.
Image source: TSMC
Almost all modern high-performance processors designed for data centers already have a multi-chip design. As demand for faster solutions grows, developers are looking to integrate even more silicon into their systems. To meet this demand, TSMC is expanding its chip packaging capabilities and making them even larger. At its North American Technology Symposium, the company showed off its 3DFabric roadmap: interposers will grow far beyond the capabilities of today’s technologies.
The current version of TSMC’s CoWoS packaging technology allows the use of interposers with an area of up to 2831 mm², which is three times larger than the maximum photomask size: the EUV standard is 858 mm², while TSMC uses 830 mm². This limit has already been reached by the AMD Instinct MI300X and NVIDIA B200 AI accelerators with two large logic chiplets and eight HBM3 or HBM3E memory stacks. However, this is no longer enough for future processors. Next year or a little later, TSMC will introduce a new CoWoS-L packaging technology with support for interposers with an area of up to 4719 mm², which is approximately 5.5 times larger than the standard photomask area. Such packaging will include up to 12 memory stacks and will require a larger substrate measuring 100 × 100 mm (10,000 mm²). Solutions built on such architecture will triple the computing performance compared to current developments. This is enough, for example, for NVIDIA Rubin accelerators with 12 HBM4 stacks, but further capacity increases will be required.
Going forward, TSMC aims to offer customers interposers up to 7,885 mm² in area—9.5 times the largest photomask possible—on a 120 x 150 mm wafer. For comparison, a typical CD case is about 125 x 142 mm. Last year, the company talked about multi-chip designs measuring 120 x 120 mm (about eight times the photomask), and the growth in that number likely reflects customer demand. Such a design would include four vertically stacked SoICs (e.g., an N2 or A16 die on top of an N3 logic die), twelve HBM4 stacks, and additional I/O dies.
TSMC has customers who demand the highest possible performance and are willing to pay for it. For them, the company offers System-on-Wafer (SoW) technology — the production of chips the size of a silicon wafer. So far, only Cerebras and Tesla have taken advantage of this opportunity, but TSMC is confident that other customers will join them. The updated SoW-X technology, based on CoWoS, will make it possible to create multi-crystal AI accelerators the size of a semiconductor wafer, on which HBM memory and optical connections can be installed. The implementation of SoW-X is planned for 2027.
Processors with a size of 9.5 mask areas or even wafer-sized chips require significant efforts in manufacturing and assembly. One of the main issues remains power supply: such chips require kilowatts of power and high current. It is becoming increasingly difficult for server manufacturers to solve this problem on their own, so it will have to be addressed at the system level. TSMC proposes to integrate monolithic integrated circuits of power management circuits (PMICs) with through-hole vertical interconnects (TSV) manufactured using N16 FinFET technology and on-wafer inductors into CoWoS-L packages with RDL (Redistribution Layer) interposers. This will allow power to be routed through the substrate, reducing the distance between power supplies and active crystals, which, in turn, will reduce parasitic resistance and improve power integrity in the system.
PMICs manufactured using N16 technology enable more precise control over power delivery to processors, says TSMC. This is especially important in multi-core and multi-chip designs where workloads can change rapidly but system stability must be maintained. The design enables fine-tuning of dynamic voltage scaling (DVS) with a given current value, achieving five times the power density of traditional approaches. Deep-trench capacitors (eDTC/DTC) embedded in the interposer or on-silicon wafer provide high decoupling density of up to 2500 nF/mm² and improve near-die power stability, ensuring reliable operation even under rapid load changes. This design improves DVS efficiency and improves transient response, both of which are critical for managing power efficiency in complex multi-core and multi-chip designs. TSMC’s approach reflects a shift toward system-level optimization: power delivery is now viewed as an integral part of the silicon, packaging, and overall design, rather than a separate function for each component.
The larger interposer size will have implications for system design, particularly in terms of package form factor. A 100 x 100 mm wafer is almost at the limit of the OAM 2.0 format (102 x 165 mm); the upcoming 120 x 150 mm wafer is already beyond that, and will likely require new standards for module packaging and board layout. In addition, such System-in-Package (SiP) packages generate a tremendous amount of heat. To address this, manufacturers are already exploring new cooling methods, including direct liquid cooling, as NVIDIA is using in the GB200/GB300 NVL72, and immersion cooling technologies to help cope with the heat output of multi-kilowatt processors. This is a challenge that TSMC cannot address at the chip or SiP level, at least not yet.