During Foundry Direct 2025, Intel unveiled a strategy to use High-NA EUV lithography in its upcoming 14A process node. While the company is actively promoting the technology, no final decision has been made on whether to use it in volume production. Instead, Intel has developed a backup plan that uses standard Low-NA EUV lithography for the 14A node. Both options will not require modifications to customer chip designs, the company said.
Image source: Rubaitul Azad / Unsplash
Meanwhile, a second High-NA EUV machine, the ASML Twinscan NXE:5000, which costs about $400 million, has already been installed at Intel’s Oregon facility, but is not yet in production due to its ongoing development. For this reason, the company is holding off on early deployment, minimizing the technology risks. Intel’s executive vice president, chief technology officer, and head of Foundry Technology and Manufacturing, Dr. Naga Chandrasekaran, emphasized that High-NA’s manufacturing parameters are in line with expectations, and the company will deploy the technology when it deems it appropriate.
Dr. Chandrasekaran said Intel already has data from 14A and 18A that demonstrates yield parity between Low-NA EUV and High-NA EUV solutions. He said the company is continuing to make technical improvements to both and is ensuring that alternative routes are available to ensure the solution chosen minimizes risk to customers and delivers the best strategic outcome.
The company plans to use High-NA EUV for only a limited number of layers in the 14A process, and the exact number is not disclosed. Other layers will use other lithography machines, including Low-NA EUV. Intel claims that using triple exposure with Low-NA instead of High-NA provides comparable results, and both routes are compatible under the design rules. This means that customers will not have to make changes to their designs, regardless of the manufacturing strategy they choose.
According to the company, yield parity between the two approaches is due to advances in modern multiple-exposure technologies, particularly in layer stacking. During the development phase, about 30,000 silicon wafers were produced using High-NA. To achieve the required pattern density using Low-NA, three consecutive exposures and up to 40 processing steps are required, while High-NA achieves the required step in a single exposure. This makes the route shorter and simpler with High-NA. It also opens up the possibility of reducing the density of metal layers, which can lead to a performance gain.
Intel did not specify whether its comparative estimates were based on exposures of full-reticule-sized dies (the mask used in projection lithography to form an image of a chip on the surface of a silicon wafer). High-NA EUV machines in their current configuration can only expose half a reticule in a single pass, so a full-reticule-sized chip requires two passes and then precise image registration. In cases where the die area is less than half a reticule, High-NA can expose in a single pass without the need for registration. In contrast, Low-NA EUV machines can expose a full-reticule-sized die in a single pass.