Intel is technically ready to package chips for TSMC customers

Demand for Nvidia’s computing accelerators is growing at an accelerated rate, and one of the reasons for the disproportionate increase in supply is the problems with chip packaging at TSMC. Intel representatives claim that TSMC customers’ solutions with CoWoS-type packaging can be easily transferred to the company’s Foveros technology.

Image Source: Intel

Mark Gardner, vice president of packaging and testing at Intel Foundry, recently said this in an email to a group of reporters, as reported by EE Times: “With Foveros, it’s able to provide a seamless transition. We’ve taken products that use CoWoS technology and directly ported them, without any design changes, to Foveros technology.”

Considering that Nvidia’s accelerator chips use the CoWoS packaging technology, there is a chance that they will be successfully transferred to the Intel Foundry pipeline, at least at the packaging and testing stage. It is important that Nvidia will thereby more quickly eliminate the need to transport silicon wafers to Taiwan, provided that they are pre-processed in the United States at the TSMC facility in Arizona. That is, political factors may play into Intel’s hands more than technological or economic ones.

According to an Intel representative, since last year the company has been releasing solutions that were initially developed for CoWoS, but were later adapted to the company’s EMIB or Foveros technologies. This is important for potential customers, Gardner added, because it does not force them to wait long for the design of their components to be adapted to the capabilities of a new contractor. Within Intel, there is a team of specialists who interact with TSMC, Samsung, SK hynix and Micron on issues of unification of design rules, allowing the use of interfaces in complex spatial arrangement of chips with minimal changes when moving from one conveyor to another.

As Gardner admitted, Intel has developed EMIB-T packaging technology using interlayer connections, which allows for the creation of chips with a three-dimensional layout and high interface bandwidth without high power consumption. Intel customers are already ready to use this technology in the next year or two. However, Intel’s contract division is still reluctant to disclose the names of its customers, and in a specific conversation with EE Times representatives, only Mediatek and AWS (Amazon) were mentioned.

TechInsights experts say that Intel has not been pushing its contract packaging capabilities very much, even though the company has not only leading technology in this area, but also spare manufacturing capacity. The trajectory of the semiconductor industry is such that packaging is important to pay attention to at the current stage, since it allows for an effective increase in component performance without visible progress in lithography.