HardwareLuxx reviewer Andreas Schilling has published images of Intel’s Arrow Lake-S desktop processor chiplets with explanations showing the internal layout of the computing unit with the cores of these processors, as well as auxiliary chiplets.
Image Source: Intel
The first image shows the entire die of the Core Ultra 200S desktop processors, with the large compute chiplet in the upper left, the I/O die at the bottom, and the SoC and iGPU chiplets on the right. The lower left and upper right are dummy chiplets that provide structural integrity to the processor die.
The chiplet with computing cores is manufactured on the basis of TSMC’s N3B (3 nm) process technology and has an area of 117,241 mm². The SoC and I/O Die blocks are manufactured on the more mature TSMC N6 (6 nm) process technology. The area of the I/O Die chiplet is 24,475 mm², and the SoC is 86,648 mm². All chiplets (or tiles, as Intel calls them) are placed on a substrate manufactured on Intel’s 22 nm FinFET process technology. Arrow Lake is the first Intel processor to use a competitor’s manufacturing technologies, with the exception of the base substrate.
The following image highlights all the additional components of the Arrow Lake secondary chiplets. The I/O Die houses the Thunderbolt 4 controllers and display PHY circuits, PCI Express and TBT4 PHY buffers, etc. The SoC houses the Display Engine controllers, media engine, additional PCIe PHY circuits, buffers, and DDR5 memory controllers. The iGPU chiplet, manufactured on TSMC’s N5P (5 nm) process, contains four Xe cores and a rendering unit based on Xe LPG (Arc Alchemist).
The final image shows the chiplet with the Arrow Lake-S processor cores in detail, which differs from other Intel processors with a hybrid architecture of big and small cores. In Arrow Lake, the company decided to place the energy-efficient E-cores between the high-performance P-cores, rather than in a separate cluster. Four of the eight Lion Cove P-cores are located on the edges of the chiplet, while the other four are in the center of the die. Four Skymont E-core clusters (four cores each) are placed between the “outer” and “inner” P-cores. This configuration is designed to reduce the thermal load when the P-cores are heavily loaded (for example, during games).
The images also show the cache layout of the Arrow Lake-S processors. Each P-core has 3 MB of L3 cache (36 MB total), and each E-core cluster has 2 MB of L2 cache. Both types of cores also share a 1.5 MB cache. Each E-core cluster is just one step away from the ring bus and from the P-core. The ring bus itself, as well as the 36 MB of L3 cache shared by the P- and E-cores (one of the key innovations of Arrow Lake), are located in the central region of the chiplet.
Arrow Lake is one of Intel’s most complex processor architectures to date, and the company’s first chiplet architecture to hit the desktop PC market. However, the first pancake was a flop: Arrow Lake-S processors disappointed with their performance due to latency issues in the bus that connects all the chiplets. Intel is trying to fix this problem with firmware updates. However, in its current form, the desktop Core Ultra 200S cannot compete with AMD Ryzen 9000 processors (especially the Ryzen 7 9800X3D) and are even inferior in gaming performance to their predecessors (in particular, the Core i9-14900K).