At the IEEE ECTC 2025 conference in Dallas in late May, Intel announced EMIB-T, an enhanced version of its chip-to-chip interconnect technology designed to support high-speed HBM4 memory and the UCIe interface. EMIB-T combines 2.5D and 3D packaging elements to provide improved power delivery and increased bandwidth between chips.
Image Source: Intel
EMIB-T (Embedded Multi-die Interconnect Bridge with TSV) is an evolution of the existing EMIB technology that adds through-silicon vias (TSVs). This allows power to be delivered directly through the bottom of the package, reducing resistance and eliminating voltage drop issues associated with previous versions. The result is more efficient integration of HBM4 or HBM4e memory and support for UCIe-A interfaces with bandwidths up to 32 Gbps and beyond.
The new technology also enables the creation of packages up to 120 x 180 mm in size, containing more than 38 bridges and more than 12 dies. The connection pitch has been reduced from 55 to 45 microns, with the prospect of reducing to 35 and even 25 microns in the future. EMIB-T is compatible with both organic and glass substrates, which opens up new opportunities for scaling and increasing the integration density.
In addition to EMIB-T, Intel introduced a new thermal spreader design that is split into a flat plate and a reinforcement element. This improves contact with the thermally conductive material and reduces the likelihood of voids by 25%. A new thermocompression bonding technology was also demonstrated, which improves reliability and yield in large-package manufacturing.
Intel is actively collaborating with leading EDA (Electronic Design Automation) software vendors, including Cadence, Siemens, and Synopsys, to create standard solutions that support EMIB-T. Additionally, Keysight announced a partnership with Intel Foundry to support EMIB-T in its chiplet design solutions, including support for UCIe 2.0 and BoW standards.
EMIB-T is a key element of Intel’s strategy to integrate components such as processors, graphics accelerators, and memory into a single package. This is especially important in the context of increasing demands for performance and energy efficiency in the AI and data center segments. The new technology also opens up opportunities for more flexible integration of components from different manufacturers, which is in line with the development of open standards in the semiconductor industry.