However, it is quite possible that silicon semiconductor units will not be completely replaced, but will be supplemented in integrated circuits with elements of a different chemical nature. Roughly speaking, the strength of silicon at the moment is in the truly enormous amounts of investment and the length of time spent on developing related technologies: in order to achieve at least somewhat comparable results using any other material, it will be necessary to spend comparable amounts of effort and money. At the same time, the most annoying drawback of silicon for microelectronics engineers, namely the almost exponentially increasing complexity of its use as a material for a transistor gate with further miniaturization of technological processes, forces them to look for a local replacement for it – precisely at the level of this individual structural semiconductor element, and not the entire production cycle as a whole. It is precisely this selective-targeted approach with the replacement of silicon only in individual areas that seems much more realistic than a complete transfer of the microprocessor industry to diamond, graphene or gallium arsenide rails.
Scattering of a free electron inside a conductor of thickness t in situations where the typical mean free path (l1, l2) is less than t/2 (left) or greater than this half-thickness (source: Nanoscale Research Letters)
⇡#A serious plane
Let us recall in the most general terms the operating principle of a transistor: electric charge flows freely or is blocked along the channel between the electrodes located on its ends, the source and drain, depending on what control voltage is applied to the gate adjacent to this channel. The smaller the production standard by which the transistor elements are manufactured, the shorter and thinner the channel is (and narrower, of course, too, but the width, if necessary, is not so difficult to vary during the design of the microcircuit, unlike the technologically determined length and thickness). At the same time, the physical dimensions of the charge carriers – free electrons and “holes”, i.e. unsubstituted positions in the outer orbitals of the atoms that form the physical structure of the channel – remain, of course, unchanged. At each successive step of miniaturization, such an important parameter for any (semi)conductor as the typical length of the free path of an electron in the channel medium is also preserved. And if this length becomes less than half the thickness of the conductive layer, each electron moving along the channel gets a noticeable chance to experience scattering at the channel boundary – and in the worst case from the point of view of organizing calculations, to “jump out” beyond its boundaries.
If the speed of such a runaway electron is high enough, it can even ionize an atom in the crystal structure of the gate, thereby slightly changing the electrical properties of the latter and disrupting the controllability of the transistor as a whole. One, two, even ten such spontaneous ionizations are not a problem, but they will inevitably accumulate during intensive operation of the transistor, which will lead to degradation of both it and the entire microprocessor structure as such – we have already described this situation in the recent material “Old Age Is No Joy (And for Silicon, Too)”. However, there is another snag, not of a cumulative nature, but of an instantaneous nature: once the charge carrier has gone beyond the channel boundary, the electric current carried along such a channel has become less by a corresponding amount. In other words, as the conductor thickness decreases to 10-15 nanometers, its electrical resistance increases exponentially – only because of the loss of an increasingly noticeable portion of the charge, the carriers of which are simply dissipated beyond the thinning channel. Somewhere from a thickness of 3 nm, the open silicon channel of a classic semiconductor transistor essentially becomes a dielectric – and this is perhaps the main limitation on further miniaturization of production standards below the conditional level of “1.4 nm”. Yes, due to various tricks, microelectronics engineers will most likely succeed in getting close to the “1 nm” process technology using classic silicon, but the problems of wear of intensively used semiconductors at the boundary reached at such a high price will certainly be disproportionately great – and will raise the question point-blankon the commercial feasibility of manufacturing both extremely small-scale silicon transistors and highly complex integrated circuits based on them.
Crystal structure of a monolayer of a transition metal dichalcogenide (source: Wikimedia Commons)
In this case, a two-dimensional material, in particular, from the category of binary chalcogenides, can become an adequate replacement for the long-suffering silicon as a transistor channel. Binary (i.e. two-component) chalcogenides, or simply dichalcogenides, are formed by atoms of metals and chalcogens – chemical elements of group VI of short form, which include, in particular, sulfur, selenium and tellurium. Of particular interest from the point of view of microelectronics are dichalcogenides with the participation of transition elements, which in English are called transition metals; hence the abbreviation TMD – transition metal dichalcogenides. Since the TMD crystal lattice atoms form bonds of two essentially different types – strong covalent and weak van der Waals – such materials naturally form a single-layer structure of repeating triple bonds “chalcogen – metal – chalcogen”, held inside the layer by strong covalent bonds. Such layers adhere to each other due to weak van der Waals interactions – and therefore it is quite simple to obtain truly two-dimensional structures of such materials in laboratory conditions (by separating the layers of the finished sample or not allowing them to adhere initially, at the stage of chemical formation), which opens up bright prospects for setting up the corresponding production on an industrial flow.
Here it is worth explaining the application of the term “two-dimensional” to a crystal structure of clearly non-zero thickness – after all, it has three atoms in height: chalcogens above and below, and metal in between. It is called two-dimensional precisely because it limits the possible mobility of the charge propagating along it to only two dimensions: only within the covalently bonded layer, but not beyond it. In turn, this limitation is due to the fact that transition metal dichalcogens are extremely reluctant to form unsaturated bonds outside the plane formed by covalent compounds. Thus, the charge carrier physically cannot escape beyond the dichalcogenide monolayer (more precisely, it does not have enough energy to do so even if the voltage between the source and drain of the transistor accelerates it to ballistic speeds), which negates the disadvantages inherent in ultra-thin silicon channels. If the maximum thickness of a silicon channel that still allows the creation of efficient transistors in practice is limited, let us recall, to approximately 3 nm, then the thickness of a monolayer of such a dichalcogenide as molybdenum disulfide (MoS2) is less than 1 nm.
A monolayer of molybdenum disulfide: on the left, under an optical microscope; on the right, under an atomic force microscope; scale bars are shown (source: Nature Nanotechnology)
⇡#Hot!
Of course, there are some subtleties here: for example, the already mentioned “unwillingness” of transition metal dichalcogenides to form unsaturated bonds with other compounds causes their high contact resistance. That is, in order to connect the source and drain electrodes to the dichalcogenide transistor channel to form an effective semiconductor device – and not just connect them, but form a contact layer through which the charge will be transferred with minimal losses – it is necessary to show remarkable engineering ingenuity. But microelectronics engineers are already finding ways to cope with this task – using, for example, semimetals such as antimony or bismuth, which simply do not have a forbidden zone. Another thing is that molybdenum, sulfur, antimony and bismuth are not the most familiar elements from the point of view of currently relevant semiconductor technologies. Of course, process engineers know how to handle them, but the problem is that the techniques and processes involved are too different from those used for silicon and germanium, which is where the semiconductor industry began and has grown to its current state. Even if all the necessary procedures can be properly coupled in the lab, scaling them up for large-scale production will take a considerable amount of time.
In addition, it is necessary to put the production of dichalcogenide monolayers themselves on an industrial scale. Over the past decades, the semiconductor industry has mastered the chemical process of metal-organic chemical vapor deposition (MOCVD). We are talking specifically about a chemical process: if in physics deposition is the formation of a solid substance from its gaseous form during condensation, then chemical deposition is a reaction of certain initial substances (precursors) in the gas phase, the main product of which is solid, and the by-products remain gaseous – and therefore can be relatively easily removed. The main product of such a reaction in the form of a very fine powder, crystals or film (down to atomic thickness) covers a solid surface: either an object that needs to be protected/reinforced by the deposited coating, or an auxiliary substrate selected so that the resulting layer can then be easily separated from it. It is by the method of chemical vapor deposition (CVD) that, by the way, titanium carbide-reinforced cutting edges of steel tools, ultra-pure polycrystalline silicon and artificial diamonds are obtained.
Formation of a molybdenum disulfide monolayer by CVD. Top left: process diagram: sulfur vapor (S) is deposited on a solid molybdenum (Mo) layer placed on a silicon substrate, which is common in microprocessor manufacturing, with an insulator in the form of an oxide layer of the same silicon; a monolayer structure is formed, as shown bottom left. On the right: the result of the described process under an electron microscope (source: Nature Nanotechnology)
MOCVD as a subtype of CVD involves the use of organometallic compounds — for the creation of, in particular, LEDs based on gallium nitride heterostructures. This technology is now well-established, and in theory, nothing prevents the formation of monolayers of transition metal dichalcogenides — TMDs — with its help. However, the most suitable reaction for this — pyrolysis — requires unbearably high (from the point of view of the silicon substrate) temperatures, up to 1000 °C, in the case of TMD-specific precursors. Worse: even if we somehow protect the silicon nanostructures located next to the TMD monolayer formed by the pyrolysis method from the effects of such extreme heat, by the very nature of this reaction, contamination of the formed film with by-products — namely, carbon atoms — is almost inevitable. It is clear that even single violations in the structure of a monolayer, the length and width of which are measured in nanometers, will inevitably change the expected properties of the transistor channel obtained in this way, which almost makes the whole idea meaningless. Other methods, such as mechanical peeling of monolayers from a TMD sample grown in the volume or molecular beam epitaxy of a transition metal dichalcogenide on a sapphire substrate, imply transferring the monolayer obtained on the side to a position verified again to a few nanometers on a rather large (300 mm in diameter) silicon wafer-blank.
Which, in turn, is a separate engineering problem – especially considering that a three-atom-thick film will have to be transferred mechanically, any creasing, breakage or other damage to a tiny section of which will obviously render the transistor created in this way unusable. Moreover, in order to transfer a thin film from the substrate where it was formed to the silicon target crystal, it is necessary to somehow secure it to the stamp that actually carries out the transfer. Usually, some adhesives are used for this, most often carbon-based, which again almost inevitably leads to contamination of the surface of even successfully transferred TMD monolayers with at least single carbon atoms. Removing them on the scale of the entire, let us repeat, 300-mm wafer is a separate procedure; painstaking and time-consuming. Intel engineers discovered that carbon contamination was responsible for the lower-than-expected performance of their successful 2D GAA transistors with an actual gate length of 25 nm in the lab—and it is clear that it is even more unacceptable in the expected large-scale production. Intel chief research engineer Kevin O’Brien bitterly stated in 2024 that even the most respectable lab results on the formation of 2D transistor channels based on TMD “show instability that terrifies technologists”—and that 2D semiconductors in general simply will not be ready for mass production until an industrial method for their production (already in the form of transistors) is discovered, mastered, and debugged.gates; i.e. either grown separately and then transferred to silicon films, or formed directly on the wafer blank) with acceptable quality.
Left: Schematic of a transistor with a 2D MoS2 channel and a high-k HfO2 layer as a gate dielectric; right: a high-electron-mobility transistor built on Schottky barriers with a pair of TMD layers differing in doping levels (source: Nature Nanotechnology)
⇡#I’m going to contact you.
Is there any point in studying dichalcogenide monolayers in application to serial semiconductor production, given how uncertain their prospects are? Researchers are sure that there is, if only for the already repeatedly stated reason of the fundamental unsuitability of silicon gates for technological processes miniaturized below the conventional “1 nm”. Of course, it is possible that in the coming years a breakthrough in the field of photonics will occur in this direction, and then the entire microprocessor industry will change radically, but this process will not be fast in any case. Classical semiconductors still have the advantage of decades of fine-tuned technological processes and a huge industry already operating at full capacity – from the extraction and purification of initial substances, components of future processors, from the development of automated design tools for microcircuits with tens of billions of transistors – and to the production of photolithographs, machines for packing cut chips into cases, control and measuring equipment, etc. No matter how promising photonics may seem at the current stage of development, bringing it to a similar level of maturity will take a lot of time and will be very expensive.
On the contrary, a point modification of existing technologies — the same replacement of a silicon transistor channel with a two-dimensional one while preserving all other components of the integrated circuit in their current form — will obviously be cheaper and can be implemented faster on a mass, serial scale, which justifies the efforts of engineers and theoreticians in developing the same two-dimensional materials. Therefore, even in the absence of more or less clearly defined deadlines for the industrial launch of TMD-channel microcircuits in series, it is necessary to develop this direction so that this launch ultimately takes place as soon as possible. And for a start — until the problem of forming a two-dimensional channel in large-scale production is solved — it makes sense to remove another, no less serious, issue from the agenda. Namely: how should the contacts between the channel and the source and drain electrodes be organized? Any contact in electrical engineering is a necessary evil (since it inevitably gives rise to losses of the current passing through the connection, parasitic heating, chemical changes in the contacting areas of the conductors, etc.), and even more so in the case of semiconductor microelectronics.
Researchers from Intel and TSMC have independently concluded that transistors with a monolayer of molybdenum disulfide as a channel are best created in a gate-all-around configuration, rather than the classic FinFET used until recently (source: TSMC)
In particular, miniaturization of the technological standard implies reduction of the length of not only the transistor channel, but also its contacts — the source and drain. It is not surprising that for these semiconductor elements the previously described effect of a sharp increase in resistance upon reaching a certain size limit manifests itself in all its glory — as Wen-Chia Wu and his colleagues from TSMC established, starting from about 10 nm. At the same time, the smoother and more even (down to the atomic level of defects) the surfaces of the metal and semiconductor monolayer in contact at the point of contact are, the lower the parasitic resistance will be here — accordingly, the lower the losses will be, the less heat dissipated into space will have to be removed from the finished microcircuit, etc. Of course, there is no talk of any solder for organizing connections: such smooth surfaces should be mutually attracted by themselves, due to weak Van der Waals forces. It should probably not be surprising that scientists name bismuth, antimony and indium as the most preferable metals for this type of contact – not only are they not very typical, to put it mildly, for the serial microelectronic industry, but they are also quite low-melting (indium, for example, has a melting point of about 157 °C).
Finally, two-dimensional materials, unlike good old silicon, do not change their conductivity properties with the ease necessary to create heterogeneous semiconductors. To form zones of electron and hole conductivity on a silicon substrate, which will then become the basis for the CMOS transistor that dominates today in microprocessor production, it is enough to introduce a small number of dopant atoms into the designated areas of the wafer blank, which will correspondingly adjust the conductivity properties of the final (doped) material. This trick will not work with transition metal dichalcogenides: p-MOS will have to be formed using, for example, WSe2, and n-MOS – the already familiar MoS2 or WS2. And not just form, but properly match, again paying attention to the super-smoothness of the contact surfaces and the super-purity of the materials used – and no less than at the atomic level. It is no coincidence that microelectronics engineers increasingly quote the great Wolfgang Pauli, whose expressive words on a similar topic are known in the retelling of Manfred R. Schoeder: “God created volume; the devil invented the surface.”
Left: A diagram illustrating how, when triangular-plan MoS2 molecules are formed on a hexagonal sapphire crystal lattice substrate, two crystallographic variants of the molybdenum disulfide structure with 60° different orientations of the main axis are formed. In the center: the initial stage of growth of triangular MoS2 monolayers. Right: a plane completely filled with two crystallographic variants of molybdenum disulfide; one-dimensional boundary structures of the same compound are shown in orange (source: Pohang University of Science and Technology)
⇡#And yet it peels off
Nevertheless, it is possible to work with the surface; you just need to notice and use its inherent features to your advantage, which was proven in 2024 by South Korean researchers from the Pohang University of Science and Technology. It was noted earlier that when growing molybdenum disulfide on a sapphire substrate, the monolayer does not grow uniformly over the entire surface of the sample, but is formed by polygonal structures, in the first approximation, equilateral triangles, inside which the rows of molecules are located parallel to their neighbors, but in directions differing by 60°. This in itself is not surprising: this is a feature of the deposition of triangular molecules of one substance on the hexagonal crystal lattice of another. However, the researchers were amazed by the fact that at the boundary between two such regions with different orientations (and if the growth zones of monolayers with the same orientations merge, they simply merge, forming a polygon of a more complex shape), a monomolecular independent layer of MoS2 with a thickness of 0.4 nm and a length of up to several tens of micrometers appears.
Isolated from both adjacent regions by the Kondo effect, this chain of dichalcogenide molecules is the thinnest artificially produced conductor in the world at the moment – and it is quite possible to use it to form a transistor gate, the channel of which will be formed in the familiar way from the same molybdenum disulfide. It is clear that it will be necessary to place an insulating gasket (made of aluminum oxide, for example) on top of the layer with conductors, and then form MoS2 monolayers on it, which will be destined to become the channels of such transistors, after which sources and drains made of well-conducting metals such as palladium, gold or titanium will be connected to this system. The result will be a semiconductor device made of two-dimensional and essentially one-dimensional components, physically separated in the third dimension, and there are no technical obstacles to solving such a problem. South Korean researchers have even built a demonstration assembly of 36 field-effect transistors on transition metal dichalcogenides with subnano-micron gates – although the channel length of such laboratory samples reaches 1.3 µm, since they were manufactured without the use of state-of-the-art photolithography. But as a proof of concept, this is an important step in what we hope is the right direction, since the alternative path, namely the nanometer-accurate and non-destructive transfer of separately manufactured monolayers onto a silicon substrate for their subsequent integration into classic semiconductor transistors, is, as we have already noted, an incredibly technically complex task.
Microscopic (optical) image of an assembly of 36 field-effect transistors (12 groups of 3), the gates for which are 12 independent monomolecular “wires” of MoS2; the scale bar is 200 μm. On the right, two transistor assemblies are shown with additional magnification, realizing the effect of p-conductivity due to the WSe2 monolayer and n-conductivity due to MoS2; here the scale bar is already 5 μm (source: Pohang University of Science and Technology)
Why does this particular direction seem right? Because microelectronics, which involves using electrons to transfer information, is naturally limited from below by the maximum thickness of conductors suitable for this purpose, one atom thick, and here the one-dimensional conductor (gate), although a monomolecule, is only three atoms thick; therefore, researchers are already close to the physical limit. Leaving photonics aside for now (which is in many ways more attractive for organizing calculations, especially massive and parallel ones, such as those needed for training and inference of neural network models, but with bringing it to mind there are still enough problems of its own), we have to admit that the prospects for classical three-dimensional semiconductors in terms of further miniaturization are far from brilliant. This means that if we manage to solve the problems that are weighing down the 2D semiconductor industry at least at the laboratory level in the foreseeable future, progress in the area of technological processes smaller than the conventional “1 nm” in current production terms has every chance of becoming a question of “only” the volume of investments required for this.
We have already mentioned one of such problems – this is the organization of the contact between the two-dimensional semiconductor and the metal source and drain, which create minimal resistance to the charge current. Roughly speaking, the snag here is as follows: in the semiconductor layer at its very border with the metal (and we remember that this border must be extremely smooth and tightly adherent to eliminate charge losses), the so-called Schottky potential barrier is formed due to the fact that electrons tend to move through the contact boundary into a medium with a higher work function (i.e., into one from which it is more energy-consuming to remove a charged particle). The higher this barrier, the more obstacles there are to the flow of charge through the transistor channel – therefore, for the source and drain electrodes, they try to select metals with a work function as close as possible to that characteristic of semiconductors. But here another problem arises: these metals, like nickel or even gold, are relatively refractory, which, as already emphasized, does not allow creating on the same substrate using classical photolithography methods both two-dimensional transistor channels and other elements of semiconductor circuits (for the formation of which higher temperatures are needed). Indium or tin, on the contrary, have an excessively low melting point, they will suffer already at the stage of packaging finished microcircuits in cases – there the heating reaches 300-500 °C. The solution may be the use of either gold alloys with the aforementioned tin or indium, which melt only at 450 °C, or semi-metals like antimony – they have a potential barrier in principlesignificantly lower, and melting temperatures are acceptably high.
The central 6×6 mm square contains 5931 molybdenum disulfide transistors, and this circuit is manufactured, most importantly from an economic point of view, using classical methods for silicon and other semiconductor CMOS transistors (source: Fudan University)
In the spring of 2025, a group of Chinese researchers from the School of Microelectronics at Fudan University in Shanghai reported the creation of a demonstration microchip called RV32-WUJI from almost 6,000 transistors based on molybdenum disulfide. To obtain a working microcircuit with 25 types of logic circuits, ready to execute 32-bit instructions, the open RISC-V microarchitecture was chosen. By modern standards, this is a very large-scale structure – the transistor channels in it extend for 3 µm each – but, operating at a frequency of 1 kHz, it consumes only 0.43 mW of power. The microelectronics engineers who received this TMD system consider its readiness for small-scale reproduction to be their main achievement: using equipment (including lithography machines and clean rooms of laboratory, not industrial level), it was possible to achieve more than 99% of suitable chips from each blank. This means that the prospects for scaling it up to larger series – with progressive miniaturization of two-dimensional semiconductor elements – seem quite bright.
So far, as can be seen, of the two main roads for integrating two-dimensional materials into the semiconductor industry – either using technologies that have already been well-developed on silicon, or building almost all the necessary production chains from scratch, but obviously without many restrictions that burden the germanium-silicon classics – neither seems a priori more preferable than the other. Perhaps, in the end, a third path will turn out to be the best one – for example, such a unique two-dimensional material as silicon ditelluride MoTe2, discovered ten years ago, will finally show itself, which in a single layer, without contact joints, can be used both to form a transistor channel and for a source/drain due to the manifestation of different electrically conductive properties depending on the configuration of its crystal lattice in a given area. One thing is clear: although the days of silicon are far from numbered, the inexorable Annushka of technological progress has already spilled her oil, and the closer the production standards being mastered by TSMC, Intel and Samsung get to the marketing boundary of “1 nm”, the louder the approaching tram bell sounds for silicon microelectronics.